This condition occurs when clock ID of the received pdelay response message (rcvdPdelayRespPtr->sourcePortIdentity.clockIdentity) matches the switches clockId (thisClock). The MDPdelayReq state machine is currently in the WAITING_FOR_PDELAY_INTERVAL_TIMER and is described in figure 11-8 of the IEEE 802.1AS-2001 document.
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Debug-Verbose
asCapable is %asCapable% => 0, port = %port%: rcvdPdelayRespPtr->sourcePortIdentity.clockIdentity (%rcvClock%) == thisClock (%thisClock%): WAITING_FOR_PDELAY_INTERVAL_TIMER state
| Name | Type |
|---|---|
| asCapable | uInt |
| port | SlotPort |
| rcvClock | String |
| thisClock | String |
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